1. Field of the Invention
The present invention relates to DC-to-DC power converter circuits, and more particularly, to a self-driven synchronous rectifier circuit for use with a primary drive voltage that remains at a zero voltage level during a portion of the power conduction cycle.
2. Description of Related Art
Advancements in the electronic arts have resulted in increased integration of electronic devices onto reduced circuit form factors. This trend has driven a demand for power supplies that provide relatively low supply voltages, such as less than 3.3 volts. Such low voltage power supplies tend to have lower efficiency than higher voltage supplies due in part to the voltage drops across the semiconductor devices of the power supplies. One type of power conversion scheme, known as self-driven synchronous rectification, is known in the art for providing relatively high efficiency in low output power applications.
An example of a conventional self-driven synchronous rectification circuit 10 is illustrated in FIG. 1. The self-driven synchronous rectification circuit 10 is coupled to the secondary winding 12 of a transformer, and includes first and second rectifiers 14, 16 that are each provided by MOSFET devices. The first rectifier 14 has a drain terminal connected to a first end A of the secondary winding 12 and the second rectifier 16 has a drain terminal connected to a second end B of the secondary winding. The gate terminal of the first rectifier 14 is connected to the second end B of the secondary winding 12, and the gate terminal of the second rectifier 16 is connected to the first end A of the transformer secondary. The source terminals of the first and second rectifiers 14, 16 are each coupled to ground. As shown in FIG. 1, each of the first and second rectifiers 14, 16 include a respective body diode between drain and source terminals thereof. The synchronous rectification circuit 10 has an output terminal coupled to the first end A of the secondary winding 12 through a first output storage choke 22 and to the second end B of the secondary winding through a second output storage choke 24. An output voltage (V.sub.o) may be derived across a load coupled between the output terminal and ground. A capacitor 26 is coupled between the output terminal and ground to filter high frequency components of the rectified output voltage.
The operation of the self-driven synchronous rectification circuit 10 of FIG. 1 is illustrated with respect to the driving voltage waveform of FIG. 2. In FIG. 2, the driving voltage between the A and B ends of the secondary winding 12 of the transformer (V.sub.A-B) is depicted as a series of rectangular pulses having a predetermined duty cycle that alternate between a positive voltage and a negative voltage. Significantly, the voltage V.sub.A-B remains at the zero level during transitions between the positive and negative voltage portions of the power conduction cycle. During the positive portion of the conduction cycle (i.e., time t.sub.1), the voltage at end A is positive with respect to the voltage at end B, causing the second rectifier 16 to turn on and the first rectifier 14 to turn off. This forms a current path through the transformer secondary winding 12, the first storage choke 22, and the second rectifier 16 to deliver output power to the load coupled between the output terminal and ground. Conversely, during the negative portion of the conduction cycle (i.e., time t.sub.3), the voltage at end B is positive with respect to the voltage at end A, the first rectifier 14 is turned on and the second rectifier 16 is turned off. This forms a current path through the transformer secondary winding 12, the second storage choke 24, and the first rectifier 14 to deliver output power to the load coupled between the output terminal and ground. Thus, power is delivered to the secondary side of the transformer during both the positive and negative portions of the conduction cycle. Since the current flowing to the load is twice the current in the secondary winding 12, this particular form of synchronous rectification circuit is generally known as a "current doubler."
Ideally, the power conduction cycle is a perfect square wave with no zero voltage transition periods between the positive and negative portions of the cycle. With such an idealized conduction cycle, the gate drive of the rectifiers 14, 16 is synchronized with current flow through the body diodes of the MOSFET devices. This way, very little current flows through the body diodes of the devices when the rectifiers 14, 16 are shut off. It is undesirable for the body diodes of the rectifiers 14, 16 to conduct current during a substantial portion of the power conduction cycle since they cause a voltage drop that results in substantial power loss, i.e., reduced efficiency. In practice, however, such an idealized power conduction cycle is difficult to achieve, and there are inevitably zero voltage transition periods between the positive and negative portions of the power conduction cycle. The zero voltage transition periods provide a condition in which both rectifiers are turned off while current is still flowing through the synchronous rectification circuit, causing the current to flow through the body diodes of the rectifiers.
More particularly, during the first and second transition periods between the positive and negative portions of the conduction cycle (i.e., times t.sub.2 and t.sub.4), the driving voltage V.sub.A-B is zero and both the first rectifier 14 and the second rectifier 16 are turned off. Magnetization current of the first storage choke 22 is conducted through the body diode of the first rectifier 14, and magnetization current of the second storage choke 24 is conducted through the body diode of the second rectifier 16. The conduction of magnetization current through the body diodes of the rectifiers results in a substantial efficiency reduction of the synchronous rectification circuit.
Accordingly, it would be desirable to provide a self-driven synchronous rectification circuit that can operate efficiently with a primary drive voltage that remains at a zero voltage level during a portion of the power conduction cycle.